illidan
PCAXE Addicted
- Učlanjen(a)
- 01.04.2009.
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Moja konfiguracija
CPU & cooler:
amd 5800x3d, ek nucleus cr240 dark, phanteks t30
Motherboard:
asus rog strix b550-i gaming
RAM:
g.skill trident z neo 32gb
VGA & cooler:
nvidia rtx 4070super founders edition
Display:
asus vg27aql1a
HDD:
samsung 980 pro 1tb, wd black sn770 2tb
Sound:
ifi zen dac v2, presonus eris 3.5, akg k712 pro balanced
Case:
lian li a4 h20
PSU:
corsair sf750 platinum
Mice & keyboard:
lamzu atlantis mini, kbd.fans tofu65 e-white
Internet:
optical cable
BEAVERTON, Ore. — Intel Labs says it has successfully fabricated an indium-gallium-arsenide field-effect transistor (FET) atop a silicon substrate by integrating a high-k gate stack. As in Intel's advanced silicon transistors, the high-k dielectric allowed the necessary thinning of the gate oxide without increasing gate leakage.
Transmission electron microscope image of InGaAs quantum well field-effect transistor showing high-k composite gate stack.
The resultant compound semiconductor quantum-well FET demonstrated the high carrier velocity and high drive current that make InGaAs-on-Si attractive, but it must be scaled down in size before the technology can be commercialized.
"We have succeeded in making the quantum-well transistor's gate length short—about 40 nanometers—but the contacts are still large," said Mike Mayberry, vice president of the Technology and Manufacturing Group and director of components research at Intel Labs. "Our challenge will be to engineer smaller contacts that minimize the barrier between the metallic contact and the quantum well."
Intel has been working for more than three years on compound semiconductors that integrate InGaAs transistors on silicon substrates, in a bid to capitalize on the manufacturing infrastructure of silicon semiconductors while achieving the high speed and high currents of InGaAs. Several hurdles have been cleared in the rush to commercialize III-V semiconductors on silicon substrates, including the ability to combine Si and InGaAs transistors on the same substrate and the architecting of both p- and n-type InGaAs devices.
Intel engineered a high-k dielectric for the demonstration InGaAs transistor that differs in formulation from the high-k material Intel uses for its advanced silicon transistors. The high-k dielectric uses a composite structure of 4 nm of tantalum silicon oxide atop a 2-nm barrier layer of indium-phosphorus. To retain high carrier mobility in the quantum-well FET, two buffer-layer materials—indium-aluminum-arsenide and indium-phosphorus—were required between the high-k dielectric and the quantum well.
Intel now is working on materials and architectures that will enable smaller contacts and is characterizing the quantum mechanical effects that will likely be triggered as its InGaAs quantum-well FETs are scaled down. Mayberry believes compound III-V transistors could begin to replace traditional silicon technology around 2015, but only if the integration challenges can be overcome.
Even if the scaling issues cannot be fully resolved, however, the III-V transistors will be candidates for integration with silicon for special purposes, such as enhancing silicon photonic devices and providing high-current driver transistors around a silicon chip's periphery.
Izvor: EETimes.com
Transmission electron microscope image of InGaAs quantum well field-effect transistor showing high-k composite gate stack.
The resultant compound semiconductor quantum-well FET demonstrated the high carrier velocity and high drive current that make InGaAs-on-Si attractive, but it must be scaled down in size before the technology can be commercialized.
"We have succeeded in making the quantum-well transistor's gate length short—about 40 nanometers—but the contacts are still large," said Mike Mayberry, vice president of the Technology and Manufacturing Group and director of components research at Intel Labs. "Our challenge will be to engineer smaller contacts that minimize the barrier between the metallic contact and the quantum well."
Intel has been working for more than three years on compound semiconductors that integrate InGaAs transistors on silicon substrates, in a bid to capitalize on the manufacturing infrastructure of silicon semiconductors while achieving the high speed and high currents of InGaAs. Several hurdles have been cleared in the rush to commercialize III-V semiconductors on silicon substrates, including the ability to combine Si and InGaAs transistors on the same substrate and the architecting of both p- and n-type InGaAs devices.
Intel engineered a high-k dielectric for the demonstration InGaAs transistor that differs in formulation from the high-k material Intel uses for its advanced silicon transistors. The high-k dielectric uses a composite structure of 4 nm of tantalum silicon oxide atop a 2-nm barrier layer of indium-phosphorus. To retain high carrier mobility in the quantum-well FET, two buffer-layer materials—indium-aluminum-arsenide and indium-phosphorus—were required between the high-k dielectric and the quantum well.
Intel now is working on materials and architectures that will enable smaller contacts and is characterizing the quantum mechanical effects that will likely be triggered as its InGaAs quantum-well FETs are scaled down. Mayberry believes compound III-V transistors could begin to replace traditional silicon technology around 2015, but only if the integration challenges can be overcome.
Even if the scaling issues cannot be fully resolved, however, the III-V transistors will be candidates for integration with silicon for special purposes, such as enhancing silicon photonic devices and providing high-current driver transistors around a silicon chip's periphery.
Izvor: EETimes.com
...ili cu morati ja, ali posto je sad kasno, sutra cu, ako nekog interesuje ovo. 
