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Intel tweaks high-k stack to get GaAs on silicon

illidan

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BEAVERTON, Ore. — Intel Labs says it has successfully fabricated an indium-gallium-arsenide field-effect transistor (FET) atop a silicon substrate by integrating a high-k gate stack. As in Intel's advanced silicon transistors, the high-k dielectric allowed the necessary thinning of the gate oxide without increasing gate leakage.



Transmission electron microscope image of InGaAs quantum well field-effect transistor showing high-k composite gate stack.

The resultant compound semiconductor quantum-well FET demonstrated the high carrier velocity and high drive current that make InGaAs-on-Si attractive, but it must be scaled down in size before the technology can be commercialized.

"We have succeeded in making the quantum-well transistor's gate length short—about 40 nanometers—but the contacts are still large," said Mike Mayberry, vice president of the Technology and Manufacturing Group and director of components research at Intel Labs. "Our challenge will be to engineer smaller contacts that minimize the barrier between the metallic contact and the quantum well."

Intel has been working for more than three years on compound semiconductors that integrate InGaAs transistors on silicon substrates, in a bid to capitalize on the manufacturing infrastructure of silicon semiconductors while achieving the high speed and high currents of InGaAs. Several hurdles have been cleared in the rush to commercialize III-V semiconductors on silicon substrates, including the ability to combine Si and InGaAs transistors on the same substrate and the architecting of both p- and n-type InGaAs devices.

Intel engineered a high-k dielectric for the demonstration InGaAs transistor that differs in formulation from the high-k material Intel uses for its advanced silicon transistors. The high-k dielectric uses a composite structure of 4 nm of tantalum silicon oxide atop a 2-nm barrier layer of indium-phosphorus. To retain high carrier mobility in the quantum-well FET, two buffer-layer materials—indium-aluminum-arsenide and indium-phosphorus—were required between the high-k dielectric and the quantum well.

Intel now is working on materials and architectures that will enable smaller contacts and is characterizing the quantum mechanical effects that will likely be triggered as its InGaAs quantum-well FETs are scaled down. Mayberry believes compound III-V transistors could begin to replace traditional silicon technology around 2015, but only if the integration challenges can be overcome.

Even if the scaling issues cannot be fully resolved, however, the III-V transistors will be candidates for integration with silicon for special purposes, such as enhancing silicon photonic devices and providing high-current driver transistors around a silicon chip's periphery.

Izvor: EETimes.com
 

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Aj prevedi sad to i objasni.... :rotf: ...ili cu morati ja, ali posto je sad kasno, sutra cu, ako nekog interesuje ovo. ;)
 

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ja sam i stavio da ti prevedes :d
 

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ays

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Превод је дефинитивно неопходан, јер ни са својим одличним знањем енглеског језика и техничких термина... скапирао сам само 20% написаног. :d
 

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Evo, 'vako kaze.....

Intel je u svom istrazivackom centru u Oregonu uspesno razvio indium-gallium-arsenide FET tranzistor na povrsini silicijumskog substrata integrisuci high-k dielektrik gate stek. Dakle, to je dielektrik visoke dielektricne konstante - high-k, cime je postignuto smanjenje curenja elektrona uz povecanje performansi tranzistora. Povecanje performansi je postignuto smanjivanjem tranzistorskog gejta. Problem kod ovoga je uvek isti - povecaj brzinu tranzistora, povecace ti se leakage. Da bi smanjili leakage, moraju da gejt izoluju nekim izolatorom inace ce tranzistor stalno da provodi neku parazitsku struju, pa ce biti lose definisana "nula" i velika specificna snaga po kvadratnom mikrometru, sto opet rezultuje visokom potrosnjom.



Ova mikroskopska slika Indium Gallium Arsenide "quantum well" FET tranzistora prikazuje highK kompozitni gate stek.
Quantum well znaci da se radi o atomskim velicinama, reda velicine nekoliko atoma, koji u steku (slojevitoj strukturi) sluze kao izolator. ;)

The resultant compound semiconductor quantum-well FET demonstrated the high carrier velocity and high drive current that make InGaAs-on-Si attractive, but it must be scaled down in size before the technology can be commercialized.
Rezultanta sinteze quantum well FET demonstrira vecu nosecu brzinu i vecu specificnu snagu po mikrometru, sto cini InGaAs on Si atraktivnim, ali on mora biti skaliran "na dole" da bi ova tehnologija bila komercijalizovana.

"We have succeeded in making the quantum-well transistor's gate length short—about 40 nanometers—but the contacts are still large," said Mike Mayberry, vice president of the Technology and Manufacturing Group and director of components research at Intel Labs. "Our challenge will be to engineer smaller contacts that minimize the barrier between the metallic contact and the quantum well."
Ovde kaze da su uspeli da naprave quantum-well transistor gejt velicine nekih 40 nm, sto je za danasnje pojmove veliko. Poredjenja radi, u 45nm procesu gejt je manji od toga, mozda nekih 30-35nm.
Kazu da im je izazov da konstruisu manje kontakte koji minimizuju barijeru izmedju metalnih kontakata i quantum well tranzistora.

Intel has been working for more than three years on compound semiconductors that integrate InGaAs transistors on silicon substrates, in a bid to capitalize on the manufacturing infrastructure of silicon semiconductors while achieving the high speed and high currents of InGaAs. Several hurdles have been cleared in the rush to commercialize III-V semiconductors on silicon substrates, including the ability to combine Si and InGaAs transistors on the same substrate and the architecting of both p- and n-type InGaAs devices.
Intel je radio vise od 3 godine na sintezi poluprovodnika koji integrisu InGaAs tranzistore na silicijumskim substratima u cilju da ulozi u proizvodne strukture za proizvodnju poluprovodnika koji ce dati brze i efikasnije InGaAs tranzistore. Postoji mogucnost da se kombinuju Si i InGaAs tranzistori na istom substratu, kao i mogucnost da se kombinuje p i n tip InGaAs FET-ova.

Intel engineered a high-k dielectric for the demonstration InGaAs transistor that differs in formulation from the high-k material Intel uses for its advanced silicon transistors. The high-k dielectric uses a composite structure of 4 nm of tantalum silicon oxide atop a 2-nm barrier layer of indium-phosphorus. To retain high carrier mobility in the quantum-well FET, two buffer-layer materials—indium-aluminum-arsenide and indium-phosphorus—were required between the high-k dielectric and the quantum well.
HK dielectric koristi kompozitnu strukturu debiljine 4nm tantalum silikon oksida koji se nalazi na 2 nm debelom sloju indijum-fosfora. Da bi omogucio visoku mogucnost nosivosti elektrona, koriscena su dva sloja materijala izmedju HK dielektrika i quantum well-a.

Intel now is working on materials and architectures that will enable smaller contacts and is characterizing the quantum mechanical effects that will likely be triggered as its InGaAs quantum-well FETs are scaled down. Mayberry believes compound III-V transistors could begin to replace traditional silicon technology around 2015, but only if the integration challenges can be overcome.
Intel sada radi na materijalima i arhitekturi koja ce omoguciti manje kontakte i karakteristicni efekti kvantne mehanike ce biti pokrenuti tek kada InGaAs quantum-well FET-ovi butu skalirani "na dole". Mayberry veruje da spoj III-V tranzistora ce zameniti tradicionalnu silicijumsku tehnologiju oko 2015. ,ali samo ako prevlada veci stepen integracije, odnosno smanjenja proizvodnog procesa.
Even if the scaling issues cannot be fully resolved, however, the III-V transistors will be candidates for integration with silicon for special purposes, such as enhancing silicon photonic devices and providing high-current driver transistors around a silicon chip's periphery.
Ako skaliranje ne bude reseno, III-V tranzistori ostace kandidati za integraciju na silicijumu za specijalne namene, kao na primer za poboljsanje silcijumsko fotonske uredjaje (chitaj lasere) i obezbedjivanje high-current drajver tranzistora oko periferije silicijumskih chipova.

Quantum tunelling efekat:

Elektroni se pokrecu nasuprot potencijalnoj energiji barijere, oni mogu da prodju kroz barijeru iako kineticka energija nije dovoljno velika
da se barijera srusi. Ovo se zove quantum tunneling efekat. U quantum-well FET-ovima InGaAs sloj predstavlja tu barijeru. S' obzirom da ce ovo oraditi sa veoma malim naponima ne cudi zasto je potrebno smanjivanje proizvodnog procesa da bi ovo radilo kako treba.


Field Effect Transistor: FET je tip tranzistora koji koristi elektricno polje da kontrolise stanje kanala koji prenosi naelektrisanje u poluprovodnickom vodu. Kada je kanal suzen, kretanje elektrona je smanjeno. Kada je kanal otvoren, protok je povecan. Dakle, kada se napon dovede na gate, FET provodi od source-a ka drain-u ili ne provodi, u zavosnosti od tipa tranzistora.

Vreme potrebno da se promeni iz logicke jedinice u logicku nulu i obrnuto je "switching speed".
 
Poslednja izmena:

illidan

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vecina jeste, a lepo je Fedja dole objasnio sta je quantum well (to nisam nikad cuo i znao sta je)
 

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vecina jeste, a lepo je Fedja dole objasnio sta je quantum well (to nisam nikad cuo i znao sta je)
Pitaj sta nije, mozda mogu i to da objasnim. Svako pitanje, pa i glupo je korisno. Nadam se da thread nece da se zavrsi na zahvaljivanju. ;) :sekira:
 

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Veoma zanimljiv članak, Feđa hvala za prevod. Verujem da na ovu temu imam pitanja, ali ostaviću to da se slegne :)
 

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Sustina je da kada se predje na vrlo mali proizvodni proces (ispod 12nm) moraju se uzeti u obzir kvantno-mehanicka svojstva cestica... A to je vec malo komplikovanije za objasnjavanje... Ako je neko zainteresovan, mogu da objasnim ovo sa stanovista fizike :D
 

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Sustina je da kada se predje na vrlo mali proizvodni proces (ispod 12nm) moraju se uzeti u obzir kvantno-mehanicka svojstva cestica... A to je vec malo komplikovanije za objasnjavanje... Ako je neko zainteresovan, mogu da objasnim ovo sa stanovista fizike :D
Počni pa da stigne taman kad i FFE 3deo :d
 

GIGAFAN

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Efekat tunelovanja, kao kod tunel dioda, koje se koriste pretezno u visokofrekventnim kolima, samo na mnogo manjoj skali.Greshim ?
 
Vrh